The present invention relates to electronic circuits. More specifically, the invention relates to drive circuitry that can operate at variable speeds in order not to exceed a minimum specified propagation delay.
The performance of a chip is often described as how fast one signal can cause another signal to change, such as, how fast a change at a given input can be propagated to a given output. The delay in the "path" through the chip between input and output is often specified as a maximum allowed delay value. It is usually desirable to have a path be as fast as possible under worst-case conditions, which are generally higher temperature and lower supply voltage.
In some chip designs, however, it is not desirable for a path to be too fast because this might cause timing problems. One example of such a situation involves the clock to output specification in the Peripheral Component Interconnect (PCI) standards, a family of standards maintained by the PCI Special Interest Group (information available at www.pcisig.com). In one version of a PCI standard, the CLK to signal valid delay is given a range of 2 ns minimum and 11 ns maximum for bused signals and 2 ns to 12 ns for point to point delays. In this case, designing a circuit that is as fast as possible (with a near 2 ns delay, for example) under worst-case conditions, might result in the circuit being too fast (i.e. less than 2 ns) when conditions are more favorable.
What is needed is a variable speed path that can ensure that a propagation speed designed to be as fast as possible under worst-case conditions does not become too fast under other conditions.